1. Field of the Invention
The present invention relates to a data processing system, comprising a host processing apparatus, and a storage subsystem connected thereto for storing and managing data sent from the host processing apparatus.
2. Description of the Related Art
In a data processing system having a constitution such that a host processing apparatus of a mainframe system and a disk array device or other such storage subsystem are connected together so as to be able to communicate with one another via a channel interface, the host processing apparatus, in order to process an access request for the storage subsystem, creates a chain of a plurality of channel command words (hereinafter abbreviated as CCW) comprising a command code, command parameter, and data, and sends this chain of a plurality of CCW (hereinafter referred to as a CCW chain) to the storage subsystem. Describing the CCW chain yet further, when data is transferred to the storage subsystem from the host processing apparatus, as disclosed in the “IBM 3390/9390 Storage Control Reference,” a WRITE system command is generally chained to DX (Define Extent) and LOC (LOCate Record). For example, when a single record is written to the storage subsystem, the host processing apparatus creates and sends a CCW chain in which a plurality of CCW, such as DX, LOC and WRCKD (Write, Count, Key and Data), are chained together in this order. Further, the above-mentioned DX and other commands, which precede READ and WRITE system commands, are called prefix commands.
A protocol that is widely used around the world exists as the protocol for the channel interface between the host processing apparatus and storage subsystem for a mainframe data processing system. The transmission of a CCW chain between the host processing apparatus and storage subsystem is carried out using a frame of a structure stipulated by this widely used protocol. This frame comprises a field, called an information field, this information field comprises a device header and a device information block, and the contents of the CCW (command, command parameter, and data) are set in the device information block. Further, the above-mentioned device header has a two-byte device address field, and the most-significant-byte area therein is a reserve area, and the least-significant-byte area can be used for specifying a device address.
Technology for carrying out parallel processing of a plurality of access requests directed at the same logical device inside the storage subsystem in a mainframe data processing system such as this, for example, is disclosed in Japanese Laid-open Patent No. 2001-312454.
According to the disclosure in Japanese Laid-open Patent No. 2001-312454, when a host processing apparatus generates a plurality of access requests to the same logical device, it creates a plurality of control blocks corresponding to these plurality of access requests, respectively, and then assigns different parallel access identification information to each of these plurality of control blocks. In addition, the host processing apparatus sets the address of the logical device to be accessed in the least-significant byte of the device address on the respective access request frames sent to the storage subsystem, and in the most-significant-byte reserve area sets parallel access identification information corresponding to the respective access requests. The storage subsystem, using the parallel access identification information set in the device address of the respective received access request frames, identifies a plurality of access requests for the same logical device, and in this way, parallelly processes the plurality of access requests for the same logical device.
Generally speaking, the storage subsystem manages a plurality of logical device addresses together in units called control units (hereinafter referred to as CU). As explained hereinabove, a widely used global protocol exists as the protocol for the channel interface for a mainframe data processing system, and by simply adhering to this protocol, the address of an access-targeted logical device inside the storage subsystem is set in the least-significant-byte area of the device address on an access request frame sent to the storage system from the host processing apparatus. Thus, a logical device address capable of being managed by one CU is limited to 1 byte, and accordingly, the maximum number of logical devices capable of being managed by a single CU is limited to 256.